The present disclosure relates to semiconductor structures, and more particularly to planar and fin field effect transistor (FET) structures having asymmetric source and drain regions, and methods of manufacturing the same.
The source-side external resistance and the drain-side external resistance of a field effect transistor impact the performance of the field effect transistor in different ways. For example, external resistance due to a source region or a source extension region has a significant impact both on the linear-regime drain current (Idlin) and the saturation drain current (Idsat) of a field effect transistor. In contrast, external resistance due to a drain region or a drain extension region has a significant impact on the linear-regime drain current of the field effect transistor, but does not impact the saturation drain current of the field effect transistor.
Further, reducing the overlap capacitance between a gate electrode and a drain extension region of a field effect transistor improves high frequency performance of the field effect transistor due to Miller effect. However, reducing the overlap capacitance between the gate electrode and a source extension region of the field effect transistor does not provide a corresponding benefit.
Thus, an asymmetric overlap of the gate electrode with a source extension region and with a drain extension region can provide various benefits in the performance of a field effect transistor.